1. Field of the Invention
This invention relates generally to integrated circuits, and more particularly to semiconductor devices having electrostatic discharge capabilities.
2. Description of the Related Art
Most integrated circuit applications have some type of electrostatic discharge (ESD) circuitry that is used to absorb and discharge high voltage electrostatic charges that can inadvertently destroy circuit devices that operate at relatively low voltage levels. Typically, ESD circuitry is designed in an input/output (I/O) cell that includes circuitry for applying signals from an I/O pad into a core circuitry region. The I/O cell also typically includes amplification circuitry for amplifying and driving signals that are generated within the core circuitry out to the I/O pad that may be coupled to a lead of a packaged device.
Typically, the electrostatic charge that is created and transferred by human handling is known to generate charges ranging up to 2,000 volts and greater (and up to about 1.3 Amps past a 1,500.OMEGA. resistor or more), which are then transferred (i.e., discharged) onto leads of the packaged device. Accordingly, most ESD circuits are required to absorb and discharge sufficiently high levels of charge that make up an ESD event. The model used to simulate these types of ESD events is commonly referred to as the human body model (HBM). When EDS circuits fail to absorb and discharge an ESD event, many types of catastrophic failures can occur, which include metal melting, junction breakdown, and oxide destruction. These type of failures are typically recognized right away, however, certain types of ESD damage can occur in the form of latent defects which can ultimately mature into complete or partial circuit malfunction.
FIG. 1A shows a top view of a semiconductor die 100 after it has been singulated from a semiconductor wafer. The semiconductor die 100 typically includes a core logic region 102 that is contained within a ring of input/output (I/O) cells 106. Each of the I/O cells 106 include a bond pad 108 that is used to interconnect the logic circuitry contained within the core logic region 102 and connections of a package in which the semiconductor die 100 will be contained. For example, a package may have a conductive lead connection 114 which will enable bond wires 116 to be connected between selected bond pads 108 and conductive lead connections 114. Typically, the I/O cells 106 will contain transistors which are wired to define electrostatic discharge (ESD) protection circuits, pre-driver circuits, driver circuits, input buffers, etc.
In order to meet the need for semiconductor devices that have high levels of ESD protection, the use of an ESD bus 120 has recently gained popularity. For example, when the conduction lead connection 114 provides a ground source (Vss) to a bond pad 108, the bond pad 108 is also connected to the ESD bus 120 through a ground isolation and conduction circuit 110. As will be described with reference to FIG. 1B below, the ESD bus 120 is needed in order to dissipate electrostatic charge when Vss bus cuts are implemented in order to separate different types of internal Vss buses.
Typically, a die edge seal 122 is also patterned along the periphery of a chip edge 104 of the semiconductor die. Normally, the die edge seal 122 is a metallization pattern that is formed at each metallization layer of an integrated circuit device. Accordingly, the die edge seal 122 will form a stacked plurality of metallization rings, one stacked over another, near the chip edge 104. The lowermost metallization ring of the die edge seal 122 is typically connected to the chip substrate via a suitable substrate connection. Therefore, the die edge seal 122 serves as a mechanical and electrical barrier to contaminants that may disrupt the operation of the semiconductor die 100.
FIG. 1B shows a more detailed diagram of a section of I/O cells 106 that are located along the periphery of the semiconductor die 100 of FIG. 1A. In this example, the chip edge 104 defines the boundary of the semiconductor die 100, and a plurality of conductive lead connections 114 are shown connected to bond pads 108 via bond wires 116. Also shown is the die edge seal 122 and the ESD bus 120. In this example, the ESD bus 120 is connected to selected bond pads 108 through the ground isolation and conduction circuit 110. These bond pads 108 are then respectively connected to selected internal Vss buses 130 and 130'.
In this illustration, conductive lead connection 114a provides a ground source (Vss) to the Vss bus 130. The Vss bus 130 is, in this example, a noisy Vss bus because it is connected to one or more larger transistors which are used in an ESD device 124. In a similar manner, conductive lead connection 114b may be used to provide a ground source (Vss) to another bond pad 108 that is connected to a Vss bus 130', which is a quiet Vss bus. As is well known in the art, Vss bus 130' is defined as quiet with respect to Vss bus 130 because it is routed among smaller transistors. Accordingly, the I/O cells 106 will commonly have more than one set of Vss and Vdd buses which provide ground and power to selected circuits of the I/O cells.
Because there are different types of Vss and Vdd buses running within the I/O cells 106, it is often necessary to physically separate the buses by implementing suitable "bus cuts" 128. In this manner, the noisy Vss and Vdd buses 130 and 132 will be isolated from the quiet Vss and Vdd buses 130' and 132'. Although bus cuts work well to isolate the different types of Vss and Vdd buses within the I/O cells 106, discharging electrostatic charge between one Vss bus and another Vss bus is quite difficult without using an ESD bus 120. For example, if the ESD bus 120 were not provided, the only conduction path for electrostatic charge would be through the substrate which is typically a highly resistive path (and would necessarily cause ESD damage). However, because the ESD bus 120 is coupled between the various Vss buses, any electrostatic charge that may be communicated to any one of the conductive lead connections will be discharged through the ESD bus and out of the chip via a neighboring conductive lead connection 114.
To elaborate further, assume that an ESD charge is inadvertently communicated onto the bond pad 108 from the ESD device 124. The ESD charge pictorially identified as 134 may travel from the bond pad 108 through the ground isolation and conduction circuit 110 to the ESD bus 120, through another ground isolation and conduction circuit 110, to another bond pad 108, and then discharged out to the conductive lead connection 114b via the bond wire 116.
For completeness, the I/O cells 106 also include many I/O transistors 125 which may be accessed through conductive lead connections, such as conductive lead connection 114c. The I/O transistors 125 are shown connected to the Vss bus 130 and Vdd bus 132, and is in communication with an I/O pre-driver control logic 126.
Although the use of an ESD bus 120 has been shown to be quite beneficial for discharging ESD event charges, they do require a good amount of die surface area in order to be formed along the entire periphery of the semiconductor die 100. Additionally, the die edge seal 122, which is connected to the substrate via a substrate connection 131, also has to be routed along the periphery of the semiconductor die 100. Because the cost of semiconductor devices is tied to the amount of semiconductor die used, it is of paramount importance to reduce the size of a semiconductor die without sacrificing the operational requirements of a given integrated circuit.
In view of the foregoing, there is a need for a more compact integrated circuit design that provides both the advantages of having an electrostatic discharge bus and a die edge seal, while simultaneously reducing the need for additional die surface area around the periphery of a semiconductor chip.